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| SL11RIDE SL11RIDETM USB to IDE/ATAPI Solution Data Sheet Cypress Semiconductor Corporation Document #: 38-08007 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised November 30, 2001 SL11RIDE Table of Contents 1.0 CONVENTIONS .............................................................................................................................. 5 2.0 DEFINITIONS .................................................................................................................................. 5 3.0 REFERENCES ................................................................................................................................ 5 4.0 GENERAL DESCRIPTION .............................................................................................................. 5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5.1 5.2 5.3 5.4 5.5 Overview ......................................................................................................................................... 5 Features of SL11RIDE ................................................................................................................... 5 Applications ................................................................................................................................... 5 Low Power Consumption .............................................................................................................. 5 Functions for Suspend, Resume, and Low-Power modes ........................................................ 6 PLL Clock Generator ..................................................................................................................... 6 Serial I2C Interface ......................................................................................................................... 7 Overview ......................................................................................................................................... 8 ATAPI/IDE Firmware ...................................................................................................................... 8 Windows(R) Host Drivers ................................................................................................................. 8 Mac Host Drivers ........................................................................................................................... 8 Multi Port Driver Support .............................................................................................................. 8 5.0 SOFTWARE .................................................................................................................................... 7 6.0 FIRMWARE DOWNLOAD .............................................................................................................. 9 6.1 How to Update the SL11RIDE Firmware ...................................................................................... 9 6.2 The QTUI2C Program .................................................................................................................... 9 6.2.1 Overview ................................................................................................................................................ 9 6.2.2 Usage ..................................................................................................................................................... 9 6.2.3 How to use QTUI2C.EXE .................................................................................................................... 10 7.0 MASS PRODUCTION DOWNLOAD EEPROM (I2C) ................................................................... 10 7.1 ToHex ............................................................................................................................................ 10 7.1.1 Overview .............................................................................................................................................. 10 7.1.2 Usage ................................................................................................................................................... 10 7.1.3 Example ............................................................................................................................................... 10 8.0 PHYSICAL CONNECTION ........................................................................................................... 11 8.1 SL11RIDE Chip Dimension ......................................................................................................... 11 8.2 SL11RIDE Pin Assignment and Description ............................................................................. 12 8.2.1 0SL11RIDE 40 Pin Interface Signals ................................................................................................. 14 8.2.2 Access LED Control ........................................................................................................................... 14 8.3 Package Markings ....................................................................................................................... 15 9.0 ELECTRICAL SPECIFICATION ................................................................................................... 15 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Absolute Maximum Ratings ........................................................................................................ 15 Recommended Operating Conditions ....................................................................................... 15 Crystal Requirements (XTAL1, XTAL2) ..................................................................................... 16 SL11RIDE USB Transceiver Characteristics ............................................................................. 16 SL11RIDE Reset Timing .............................................................................................................. 16 Reset Circuit ................................................................................................................................. 17 SL11RIDE PIO Read/Write Cycle ................................................................................................ 17 10.0 APPENDIX .................................................................................................................................. 17 10.1 SL11RIDE Pin Translation: 36-Pin-40-Pin Signals ................................................................. 17 Document #: 38-08007 Rev. ** Page 2 of 27 SL11RIDE Table of Contents (continued) 10.2 10.3 10.4 10.5 10.6 10.7 10.8 SL11RIDE Pin Translation: 40-Pin-44-Pin Signals ................................................................. 18 SL11RIDE Pin Translation: 40-Pin-50-Pin SLIM Connector .................................................. 19 CLIK 50-Pin Connect with SL11RIDE ....................................................................................... 20 SL11RIDE Pin Translation: 40-Pin-50-Pin CF Card Signals .................................................. 20 Fast EPP Pin Assignment and Description ............................................................................. 22 Design ATAPI/IDE Device Behaves Like Floppy Disk Drive .................................................. 24 CPU Speed Control .................................................................................................................... 25 10.8.1 Speed Control Register (0xC008: R/W) .......................................................................................... 25 11.0 REVISION HISTORY ................................................................................................................... 27 List of Figures Figure 4-1. USBPU Pull-up Connection Example ............................................................................. 6 Figure 4-2. Full-Speed 48-MHz Crystal Circuit .................................................................................. 6 Figure 4-3. 12-MHz Crystal Circuits ................................................................................................... 7 Figure 4-4. I2C 2-Kbyte Connection ................................................................................................... 7 Figure 5-1. General Views ................................................................................................................... 8 Figure 5-2. Multi-portable Drivers ...................................................................................................... 9 Figure 9-1. Reset Circuit Sample ...................................................................................................... 17 Figure 10-1. Compact Flash Design Note ........................................................................................ 25 List of Tables Table 5-1. Windows Host Software OS Compatibility ...................................................................... 8 Table 5-2. Mac Host Software OS Compatibility ............................................................................... 8 Table 8-1. 40-pin Connector Interface Signals ................................................................................ 14 Table 10-1. 36-pin to 40-pin Interface Signals ................................................................................. 17 Table 10-2. SL11RIDE Pin Translation: 40-Pin-44-Pin Signals ..................................................... 18 Table 10-3. SL11RIDE Pin Translation: 40-Pin-50-Pin SLIM Signals ............................................ 19 Table 10-4. SL11RIDE Pin Translation: 40-Pin-50-Pin Signals ..................................................... 20 Table 10-5. Fast EPP Pin Assignment and Description ................................................................. 22 Table 10-6. Power Switch Operation ................................................................................................ 25 Table 10-7. Compact Flash Design .................................................................................................. 25 Document #: 38-08007 Rev. ** Page 3 of 27 SL11RIDE License Agreement Use of this document and the intellectual properties contained herein indicates acceptance of the following License Agreement. If you do not accept the terms of this License Agreement, do not use this document, or the associated intellectual properties, or any other material you received in association with this product, and return this document and the associated materials within fifteen (15) days to Cypress Semiconductor Corporation (CY) or CY's authorized distributor from whom you purchased the product. 1. You can only legally obtain CY's intellectual properties contained in this document through CY or its authorized distributors. 2. You are granted a nontransferable license to use and to incorporate CY's intellectual properties contained in this document into your product. The product may be either for your own use or for sale. 3. You may not reverse-engineer the SL11RIDE or otherwise attempt to discover the designs of SL11RIDE. 4. You may not assign, distribute, sell, transfer, or disclose CY's intellectual properties contained in this document to any other person or entity. 5. This license terminates if you fail to comply with any of the provisions of this Agreement. You agree upon termination to destroy this document, stop using the intellectual properties contained in this document and any of its modification and incorporated or merged portions in any form, and destroy any unused SL11RIDE chips. Warranty Disclaimer and Limited Liability Cypress Semiconductor Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Cypress's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Cypress Semiconductor are granted by the Company in connection with the sale of Cypress products, expressly or by implication. Cypress's products are not authorized for use as critical components in life support devices or systems. SL11RIDE is a trademark of Cypress Semiconductor Corporation. All other product names are trademarks are registered trademarks of their respective owners. Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Pentium is a registered trademark of Intel Corporation. Windows is a registered trademark of Microsoft Corporation. Document #: 38-08007 Rev. ** Page 4 of 27 SL11RIDE 1.0 1,2,3,4 Dh, 1Fh, 39h 0101b, 010101b bRequest, n Conventions Numbers without annotation are decimal Hexadecimal numbers are followed by an "h" Binary numbers are followed by a "b" Words in italics indicated terms defined by USB Specification or by this Specification 2.0 I2C Definitions Two-wire Serial flash EEPROM interface The SL11R-IDE is 16-bit RISC USB processor, which provides USB to ATAPI/IDE interface on a single chip Universal Serial Bus Utilities tools for ScanLogic 16-bit RISC USB processor Compact Flash SL11RIDE USB QTOOLS CF 3.0 References [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5) 4.0 4.1 General Description Overview The SL11RIDE is a low-cost, high-speed Universal Serial Bus RISC-based Controller board. It contains a 16-bit RISC processor with built-in SL11RIDE ROM to greatly reduce firmware development efforts. Its serial flash EEPROM interface offers low-cost storage for USB device configuration and customer product specific functions. New functions can be programmed into the I2C by downloading them from a USB Host PC. This unique architecture provides the ability to upgrade products, in the field, without changing the peripheral hardware. 4.2 Features of SL11RIDE * Two-wire serial EEPROM (I2C) interface port, with SL11RIDE ROM firmware support, to allow on board flash EEPROM programming * Supports 12-MHz/48-MHz external crystal or clock * 6Kx8 internal Mask ROM with built-in BIOS * Supports up to the maximum USB transfer rate of 12 Mbits/sec * Power source requires only 3.3V, and it can be powered via a USB host PC or a Hub * Resume, Suspend, and Low-power modes are available * Includes the necessary firmware to function as a USB to IDE/ATAPI controller 4.3 Applications Cypress offers a Developer's Kit with all its product lines. These Developer's Kits include: ATAPI/IDE firmware, multiple peripheral Mini-port class drivers for Windows98/2000, MAC 8.6 or higher available object code, a complete ATAPI/IDE solution reference design, and a demo board. The SL11RIDE offers solutions for interfacing USB to IDE/ATAPI peripheral products including HDD, CD-ROM, CD-R/RW, ZIP drives, LS120, MO drives, Compact Flash, Disk on Chip, Tape drives, Smart Media cards, ORB, and CLIK, and MicroDrives. 4.4 Low Power Consumption The SL11RIDE offers various power consumption modes. The maximum power consumption at 48-MHz operation, including USB, is less then 30 mA, but on the average it consumes around 10 mA. The following are measurements taken under different setups of the SL11RIDE: Idle Mode: During Reset: Post Reset: 2.0 mA (USB is on, CPU runs at 48 MHz) 3.0 mA (Reset is held LOW) 12.5 mA typical at 48 MHz Document #: 38-08007 Rev. ** Page 5 of 27 SL11RIDE Max at 4 MHz CPU speed: 4.0 mA (USB is on) Max at 32 MHz CPU speed: 25.0 mA (USB is on) Max at 48 MHz CPU speed: 30.0 mA (USB is on) 4.5 Functions for Suspend, Resume, and Low-Power modes The SL11RIDE's CPU supports suspend, resume, and CPU low power mode. The SL11RIDE BIOS assigns USBPU for the USB DATA+ line pull-up, which simulates USB cable removal or insertion while USB power is still applied to the board. USBPU 1.5 k USB type B Connector 36 36 1 2 3 4 VCC DD+ GND Figure 4-1. USBPU Pull-up Connection Example 4.6 PLL Clock Generator A 48-MHz external crystal can be used with the SL11RIDE. Two pins, X1 and X2, are provided to connect a low-cost crystal circuit to the device. Circuitry is provided to generate the internal clock requirements of the device. If an external 48-MHz clock is available in the application, it may be used instead of the crystal circuit by connecting directly to the X1 input pin. X1 X2 Rf 1M Rs 100 X1 Cbk 0.01 uF 48 MHz, series, 20-pF load Lin 3.3 H Cout 22 pF Figure 4-2. Full-Speed 48-MHz Crystal Circuit Document #: 38-08007 Rev. ** Page 6 of 27 SL11RIDE X1 X2 Rf 1M Rs 100 X1 12 MHz , series, 20-pF load Cin 22 pF Cout 22 pF Figure 4-3. 12-MHz Crystal Circuits Note: You need to set bit C2 =1 from configuration address (0xC006). See section 10.8 for CPU speed control. 4.7 Serial I2C Interface The SL11RIDE provides an interface to an external serial flash EEPROM. A variety of serial EEPROM formats can be supported. Currently the SL11RIDE firmware supports the two-wire serial flash EEPROM type. It can be used for field product upgrades if needed. The recommended serial EEPROM device is a two-wire Serial CMOS EEPROM (AT24LCXX Device Family). Currently, the SL11RIDE allows writing to EEPROM, up to 2 KBytes, using a 16-Kbit I2C device (i.e. AT24LC16B/SN). The USB vendor/device configuration can be programmed and stored into the external EEPROM device. On power-up, the contents of the EEPROM will be downloaded into RAM. The advantage of the EEPROM interface is both cost and space saving compared with using an external 8-bit PROM/EPROM. VCC EEPROM 1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 SCL SDA 1.5-5K 0.1 F AT24C16 Figure 4-4. I2C 2-Kbyte Connection Note: You can choose either a 3.3V or a 5.0V EEPROM. 5.0 Software The SL11RIDE software is USB Specification and USB Mass Storage Class Bulk-Only Transport version 1.0 compliant in the final release. In the meantime, it will try to track changes to the USB Mass Storage Class Bulk-Only Transport as closely as possible. The interface to the host PC is USB, which allows true Plug-and-Play (PnP). The requirement for Operating System (OS) on the host PC side is Win98/2000 or MAC. Document #: 38-08007 Rev. ** Page 7 of 27 SL11RIDE 5.1 Overview This document provides a complete outline description of the SL11RIDE firmware and host mini-port driver under Win98/2000, which supports Bulk Only Transport between host PC and SL11RIDE. See Figure 5-1 for details. Scanlogic USB to ATAPI/IDE System Host USB PC 86% 3RUW SL11RIDE 86% External ATAPI/IDE Peripherals Figure 5-1. General Views 5.2 ATAPI/IDE Firmware SL11RIDE's firmware supports both ATAPI and IDE devices. The firmware is USB Mass Storage Class compliant, which supports multiple Operating Systems such as Windows(R)98/2000 and Mac. 5.3 Windows(R) Host Drivers The WDM and MPD device drivers operate under Windows 98. Win2000 doesn't need any special drivers. See Table 5-1 for more detail. Table 5-1. Windows Host Software OS Compatibility Operation System Windows98 Windows98SE Window2000 Windows NT USB / / -First Edition from Microsoft Second Edition from Microsoft WIN2000 beta from Microsoft NT 4.0 does not support USB Note 5.4 Mac Host Drivers Cypress does not support end-user firmware updates under the Mac OS. OEM customers must download firmware from MS-DOS. Table 5-2. Mac Host Software OS Compatibility Operating System G3: OS8.6, OS9 iMAC: OS8.6, OS9 Laptop: OS8.6, OS9 USB / --G3 iMAC G3 Laptop Note 5.5 Multi Port Driver Support Currently SL11RIDE mini-port driver is a multi-device driver for ATAPI/IDE peripherals. This driver supports up to 7 ATAPI/IDE devices, which connect via a USB Hub. See Figure 5-2 for details. Document #: 38-08007 Rev. ** Page 8 of 27 SL11RIDE PC WIN98/2000 OS CiAr y +8% 3RUW 3RUW 3RUW 3RUW 3RUW 3RUW 3RUW +'' &) 02 &' 0286( &'5: /6 Figure 5-2. Multi-portable Drivers Note: * These devices must be self-powered since the Hub cannot provide enough current to each ATAPI/IDE device. * We recommend that a PC for this configuration be at least a 300-MHz Pentium(R) II with 64 Mbyte RAM 6.0 6.1 Firmware Download How to Update the SL11RIDE Firmware The firmware on the EEPROM doesn't have to be changed after it is downloaded for the first time. If it needs to be changed during testing or for future firmware updates, this can be done from a PC using the USB port. The need to change firmware to switch between an ATAPI device and an IDE device will be removed in a future release. 6.2 6.2.1 The QTUI2C Program Overview The QTUI2C program is used to program the I2C EEPROM that is externally connected to the SL11RIDE chip. This allows programming the I2C with data alone, such as the USB data descriptors. The SL11RIDE will scan the I2C for a valid signature before attempting to load the code and/or data to the internal/external RAM. To program the file, the input filename without the extension is required. The QTUI2C will create a file "MAKEENH.BIN" based on the Object input file. This "MAKEENH.BIN" file will contain the fix-up (.bin) information and it will have a proper format that is defined on the SL11RIDE BIOS specification. 6.2.2 QTUI2C Usage Document #: 38-08007 Rev. ** Page 9 of 27 SL11RIDE Where: The QTOOLS utilities are in directory C:\Program Files\ScanLogic\USB2IDE\bin. * qtui2c zero.bin ; You need to erase all program from I2C each time you download a new program. * qtui2c cidexxx.bin ; Program ATAPI and IDE firmware into I2C 7.0 7.1 7.1.1 Mass Production Download EEPROM (I2C) ToHex Overview This program converts the Binary output file (. bin) to the INTEL HEX format. This INTEL HEX format will be used for programming the PROM on the DATAIO. 7.1.2 Where: Infilespec.bin Outfilespec.hex Offset [h|l] is the Binary output file produced by the QTASM is the INTEL HEX output file produced by the TOHEX program is valid from 0x0000 to 0xFFFF. Default is 0x0000. `h' is selected HIGH PROM output file. `l' is selected LOW PROM output file. Without this input the default INTEL HEX output file will be stored into the single 8-bit PROM. Example cidexxx.bin cidexxx.hex ; Create INTEL HEX format for ATAPI device Usage TOHEX 7.1.3 TOHEX Document #: 38-08007 Rev. ** Page 10 of 27 SL11RIDE 8.0 8.1 Physical Connection SL11RIDE Chip Dimension The SL11RIDE's Package type is 100 PQFP. Document #: 38-08007 Rev. ** Page 11 of 27 SL11RIDE 8.2 SL11RIDE Pin Assignment and Description Pin Assignment and Description Pin Name VDD GND X1 X2 VDD GND TEST nRESET VDD VDD SCL SDA USBPU TXD GND GND RXD PWC INTRQ/ HW_RESET/ RB DASP/ WP IOWD CS0 CS1 IORD C_DET VDD A2 A1 A0 GND D15 D14 D13 D12 D 11 GPIO27 GPIO26 GPIO25 GPIO31 GPIO30 GPIO29 GPIO28 GPIO name Pin No. 1 14 15 16 17 40 44 48 50 51 60 61 62 63 64 65 66 67 68 Pin Type Power GND Input Output Power GND Input Input Power Power Bidir Bidir Bidir Output GND GND Input Bidir Bidir +3.3 VDC supply Digital ground External 48-MHz Crystal or Clock input[2] External crystal output. Not connect if X1 is used for clock input +3.3 VDC supply[1] Digital ground NC--No Connection, MFG test only[3] Master Reset. SL11RIDE Device active LOW reset input +3.3 VDC supply[1] +3.3 VDC supply[1] Serial Flash EEPROM clock Serial Flash EPROM data[4] USB turn on/off D+ pull-up resistor UART TXD Digital ground Digital ground UART RXD Power control[5] Interrupt triggers in the SL11RIDE processor, or define for Hardware Reset for CF[6] Device Active Present, or define for Write Protect for Smart Media[6] IOWD--Write uses to indicate IDE write data transfer Chip Select 0 Chip Select 1 or user defines Smart media card detect IORD uses to indicate IDE read data transfer C_DET uses to detect CF +3.3 VDC Supply[1] Address bit 2 Address bit 1 Address bit 0 Digital ground. DATA port bit 15 DATA port bit 14 DATA port bit 13 DATA port bit 12 DATA port bit 11 Page 12 of 27 [1] SL11RIDE Pin Description GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 75 GPIO18 GPIO17 GPIO16 79 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Bidir Bidir Bidir Bidir Bidir Bidir Power Bidir Bidir Bidir GND Bidir Bidir Bidir Bidir Bidir Document #: 38-08007 Rev. ** SL11RIDE Pin Assignment and Description (continued) Pin Name D10 D9 VDD1 DATA+ DATAUSB_GND D8 D7 D6 D5 D4 D3 D2 D1 D0 VDD GPIO name GPIO10 GPIO9 87 88 89 90 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 100 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Type Bidir Bidir Power Bidir Bidir GND Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Power DATA port bit 10 DATA port bit 9 USB +3.3 VDC Supply[1] USB Differential DATA Signal High Side. USB Differential DATA Signal Low Side. USB Digital Ground. DATA port bit 8 DATA port bit 7 DATA port bit 6 DATA port bit 5 DATA port bit 4 DATA port bit 3 DATA port bit 2 DATA port bit 1 DATA port bit 0 +3.3 VDC Supply[1] SL11RIDE Pin Description Notes: 1. All +3.3VDC must use a 0.1-F bypass capacitor and these capacitors must be placed near the SL11RIDE chip. 2. 48-MHz Crystal or oscillator has to use a capacitor 0.1 F to filter output signals. It must be placed at least 3/4" from 3.3V, 5.0V or a USB connector 3. All pins not shown (NC pins and reserved pins) should not be connected or used for other purposes. 4. This signal requires a 1- to 5-k pull-up. 5. GPIO26: This signal can be used for device low power mode. It will turn off or disable external powers to the peripheral in suspend mode. Once USB power is resumed, external power can be enabled again 6. GPIO25 can be used as INTRQ/HW_RESET/RB and GPIO24 can be used as DASP/WP signals. These signals are used for CF and Smart Media to exchange media cards or insert/remove media while power is still supplied to the board. Document #: 38-08007 Rev. ** Page 13 of 27 SL11RIDE 8.2.1 0SL11RIDE 40 Pin Interface Signals Table 8-1. 40-pin Connector Interface Signals SL11RIDE Signal RESET D7 D6 D5 D4 D3 D2 D1 D0 GND PU [7] IDE Signal RESET DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 GND DMARQ DIOW DIOR IORDY DMACK INTRQ DA1 DA0 CS0 DASP Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IDE Signal GND DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 Key GND GND GND CSEL GND IOCS16 PDIAG DA2 CS1 GND SL11RIDE Signal GND D8 D9 D10 D11 D12 D13 D14 D15 (See Note 8) GND GND GND PD[9] GND PU PU A2 CS1 GND IOWD IORD PU[7] PU[7] INTRQ A1 A0 CS0 DASP Notes: 7. PU: These signals need 10 k pull-up. 8. The Key pin must be not be connected. 9. PD: CSEL connects to GND for default Master and Slave modes. 8.2.2 Access LED Control The CS0 uses LED access control. You can define the value of R1. 3.3V OR VCC R1 D1 LED CS0 Document #: 38-08007 Rev. ** Page 14 of 27 SL11RIDE 8.3 Package Markings SL11R-IDE YYWWSQFP-1.2 XXXX YYWW = Date code XXXX = Product code 9.0 9.1 Electrical Specification Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL11RIDE. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature Power Supply Voltage (VDD) Power Supply Voltage (VDD1) -40C to 125C 3.3V10% 3.3V10% 9.2 Recommended Operating Conditions Parameter Min. 3.0V 3.0V 0C Typical 3.3V Max 3.6V 3.6V 65C Power Supply Voltage, VDD Power Supply Voltage, VDD1 Operating Temperature Document #: 38-08007 Rev. ** Page 15 of 27 SL11RIDE 9.3 Crystal Requirements (XTAL1, XTAL2) (XTAL1, XTAL2) Min. 0C 48 MHz 20 ppm 100 ppm 30 ppm Typical Max. 65C Crystal Requirements, Operating Temperature Range Series Resonant Frequency Frequency Drift over Temperature Temperature Stability Accuracy of Adjustment Mode of Vibration Series Resistance Load Capacitance Shunt Capacitance Driver Level 3rd Overtone 100 20 pF 3 pF 20 W 7 pF 5 mW 9.4 SL11RIDE USB Transceiver Characteristics Parameter Description Hysteresis On Input (Data+, Data-) USB Input Voltage HIGH USB Input Voltage LOW USB Output Voltage HIGH USB Output Voltage LOW Output Impedance HIGH STATE Output Impedance LOW STATE Transceiver Supply p-p Current (3.3V) 24 24 0.8V 2.2V 0.7V 43 43 < 220 A Min. 0.1V 1.5V 1.3V Typical[10] Max. 200 mV 2.0V VIHYS VUSBIH VUSBIL VUSBOH VUSBOL ZUSBH[11] ZUSBL[11] IUSB Notes: 10. All typical values are VDD2 = 3.3 V and TAMB= 25C. 11. ZUSBX Impedance Values includes an external resistor of 24 -- 43 Ohms 1% 9.5 SL11RIDE Reset Timing The nRESET signal from the SL11RIDE chip resets the disk drive. It forces an initialization to occur identical to that after power-up. treset nRESET VDD nRD or nWR t RPU V max V RH tioact RESET TIMING Document #: 38-08007 Rev. ** Page 16 of 27 SL11RIDE Parameter VCC tRPU Vmax VRH treset tioact Description Operating Voltage Range Time Reset Pull up Voltage reach max Voltage Reset High nRESET Pulse width nRESET high to nRD Min. Typical Max. 5.5V 150 ms VDD - 0.7V 3.0V 16 clocks 16 clocks Note: Clock is 48 MHz nominal. 9.6 Reset Circuit 6/5,'( Microcontroller 9&& ) *1' 0& 3 5(6(7 Figure 9-1. Reset Circuit Sample 9.7 SL11RIDE PIO Read/Write Cycle At power-up and during Read/Write Cycles, the SL11RIDE uses PIO mode 2 timing for the data transfer from/to device. See chapter 10 in the section 10.2.2 of [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5) for more detail. 10.0 Appendix This is a pin translation of SL11RIDE signals to 36, 44, 50, and 68 of the Storage Device Class, which is based on the latest AT Attachment specification and Compact Flash Specification Version 1.4. These signals connect directly to the ATAPI/IDE devices. If you intend to design for a long IDE cable, then you have to use RC Termination. See [ref 1] AT Attachment with Packet Interface Extension (ATA/ATAPI-5). 10.1 SL11RIDE Pin Translation: 36-Pin-40-Pin Signals Table 10-1. 36-pin to 40-pin Interface Signals SL11RIDE Signal GND nRESET D8 D7 D9 D6 D10 36-Pin Signal GND RESET D8 D7 D9 D6 D10 36-Pin 1 2 3 4 5 6 7 Translates 40-Pin 2 1 4 3 6 5 8 Document #: 38-08007 Rev. ** Page 17 of 27 SL11RIDE Table 10-1. 36-pin to 40-pin Interface Signals (continued) SL11RIDE Signal D5 D11 D4 D12 D3 D13 D2 D14 D1 D15 D0 PU[7] IOWD IORD PU [7] [7] 36-Pin Signal D5 D11 D4 D12 D3 D13 D2 D14 D1 D15 D0 DMARQ IOWR IORD IORDY DMACK IRQ IOCS16 A1 GND A0 A2 CS0 CS1 GND +5V GND +5V GND 36-Pin 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Translates 40-Pin 7 10 9 12 11 14 13 16 15 18 35 NC 23 25 27 NC 31 32 33 19 35 36 37 38 22 VCC 24 VCC 26 PU INTRQ PU[7] A1 GND A0 A2 CS0 CS1 GND VCC GND VCC GND 10.2 SL11RIDE Pin Translation: 40-Pin-44-Pin Signals Table 10-2. SL11RIDE Pin Translation: 40-Pin-44-Pin Signals IDE Signal Pin A C E nRESET DD7 Document #: 38-08007 Rev. ** 1 3 Pin B D F 2 4 IDE Signal (See Note 12) (See Note 12) (See Note 12) GND DD8 Page 18 of 27 SL11RIDE Table 10-2. SL11RIDE Pin Translation: 40-Pin-44-Pin Signals (continued) IDE Signal DD6 DD5 DD4 DD3 DD2 DD1 DD0 GND DMARQ[15] IOWD IORD IORDY [15] Pin 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Pin 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 IDE Signal DD9 DD10 DD11 DD12 DD13 DD14 DD15 Key[13] GND GND GND CSEL[14] GND IOCS16[15] PDIAG[15] DA2 CS1 GND +5V TYPE DMACK[15] INTRQ DA1 DA0 CS0 DASP +5V GND Notes: 12. A--F: Pins that are additional to those of the 40-pin connector. 13. The Key pin must be not connected. 14. CSEL connect to GND for default Master and Slave modes. 15. These signals need a 10k pull-up. 10.3 SL11RIDE Pin Translation: 40-Pin-50-Pin SLIM Connector The SLIM connector is a new connector that is used for CD-ROM, CD-RW, and ZIP drives. Table 10-3. SL11RIDE Pin Translation: 40-Pin-50-Pin SLIM Signals SL11RIDE Signals NC GND nRESET D7 D6 D5 D4 D3 D2 D1 D0 SLIM Signals LOUT AGND RESET DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 Pin 1 3 5 7 9 11 13 15 17 19 21 Pin 2 4 6 8 10 12 14 16 18 20 22 SLIM Signals ROUT NC DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DMARQ NC NC D8 D9 D10 D11 D12 D13 D14 D15 PU[7] Page 19 of 27 SL11RIDE Signals Document #: 38-08007 Rev. ** SL11RIDE Table 10-3. SL11RIDE Pin Translation: 40-Pin-50-Pin SLIM Signals (continued) SL11RIDE Signals GND IOWD PU[7] INTRQ A1 A0 CS0 DASP VCC VCC GND GND PD [16] SLIM Signals GND DIOW IORDY INTRQ DA1 DA0 CS0 DASP +5V +5V GND GND CSEL Reserved Pin 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Pin 24 26 28 30 32 34 36 38 40 42 44 46 48 50 SLIM Signals DIOR- GND DMACK IOCS16 PDIAG DA2 CS1- +5V +5V +5V GND GND GND Reserved IORD GND PU[7] PU[7] PU[7] A2 CS1 VCC VCC VCC GND GND GND NC SL11RIDE Signals NC Note: 16. PD: CSEL connect to GND for Master and Slave mode 10.4 CLIK 50-Pin Connect with SL11RIDE The CLIK can connect directly to the SL11RIDE chip for integration solution or can interface with the SL11RIDE via a PCMCIA card. Note: * User can define STATUS LED. 10.5 SL11RIDE Pin Translation: 40-Pin-50-Pin CF Card Signals Table 10-4. SL11RIDE Pin Translation: 40-Pin-50-Pin Signals SL11RIDE Pin VCC VCC nRESET D7 D6 D5 D4 D3 D2 D1 D0 GND PU IOWD CLIK Signal VCC 5V HRSTD HDD7 HDD6 HDD5 HDD4 HDD3 HDD2 HDD1 HDD0 GND DREOO IOWI Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 Pin 2 4 6 8 1012 14 16 18 20 22 24 26 28 CLIK Signal GND GND X HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 KEYED GND GND SL11RIDE Pin GND GND X D8 D9 D10 D11 D12 D13 D14 D15 NC GND GND Document #: 38-08007 Rev. ** Page 20 of 27 SL11RIDE Table 10-4. SL11RIDE Pin Translation: 40-Pin-50-Pin Signals (continued) SL11RIDE Pin IORD PU PU INTRQ A1 A0 CS0 DASP VCC GND with 22 GND with 22 SL11RIDE Signals GND D4 D6 CS0 GND GND PVCC[17] GND GND A1 D0 D2 GND D11 D13 D15 GND IOWD PU[7] PD[14] PWC_RESET Not Connect PU[7] D8 D10 Notes: 17. PVCC= 5VDC from power switch CLIK Signal IORI IOCHROYI DACK1 IA01 HA10 HA00 HCS00 DASPI VCC TXD ATA MODE CF Signals GND D4 D6 CE1 OE A8 VCC A5 A3 A1 D0 D2 CD2 D11 D13 D15 VS1 IOWR IREQ CSEL RESET INPACK BVD2 D8 D10 Pin 29 31 33 35 37 39 41 43 45 47 49 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Pin 30 32 34 36 38 40 42 44 46 48 50 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 CLIK Signal GND CESEL GND IOCSI61 POIAG HA20 HCS10 GND GND RXD STATUS LED CF Signals D3 D5 D7 A10 A9 A7 A6 A4 A2 A0 D1 IOSI16 CD1 D12 D14 CE2 IORD WE VCC VS2 WAIT REG BVD1 D9 GND SL11RIDE Pin GND GND with 22 GND PU PU A2 CS1 GND GND GND with 22 Note 7 SL11RIDE Signals D3 D5 D7 GND GND GND GND GND A2 A0 D1 PU[7] C_DET D12 D14 PU[7] IORD PVCC[17] PVCC[17] GND PU[7] PU[7] PU[7] D9 GND Document #: 38-08007 Rev. ** Page 21 of 27 SL11RIDE 10.6 Fast EPP Pin Assignment and Description Table 10-5. Fast EPP Pin Assignment and Description Pin Name VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 GND X1 X2 VDD D12 D13 D14 D15 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 GPIO Pins Pin Type Power Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir GND Input Output Power Bidir Bidir Bidir Bidir Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output GPIO & Fast EPP Pin Chip Revision 1.1 +3.3 VDC Supply External Memory Data Bus, Data0 External Memory Data Bus, Data1 External Memory Data Bus, Data2 External Memory Data Bus, Data3 External Memory Data Bus, Data4 External Memory Data Bus, Data5 External Memory Data Bus, Data6 External Memory Data Bus, Data7 External Memory Data Bus, Data8 External Memory Data Bus, Data9 External Memory Data Bus, Data10 External Memory Data Bus, Data11 Digital ground. External 48-MHz Crystal or Clock Input. External crystal output. No connection when X1 is used for clock input +3.3 VDC Supply External Memory Data Bus, Data12 External Memory Data Bus, Data13 External Memory Data Bus, Data14 External Memory Data Bus, Data15 External Memory Address Bus, A20 External Memory Address Bus, A19 External Memory Address Bus, A18 External Memory Address Bus, A17 External Memory Address Bus, A16 External Memory Address Bus, A15 External Memory Address Bus, A14 External Memory Address Bus, A13 External Memory Address Bus, A12 External Memory Address Bus, A11 External Memory Address Bus, A10 External Memory Address Bus, A9 External Memory Address Bus, A8 External Memory Address Bus, A7 External Memory Address Bus, A6 External Memory Address Bus, A5 Page 22 of 27 Document #: 38-08007 Rev. ** SL11RIDE Table 10-5. Fast EPP Pin Assignment and Description (continued) Pin Name A4 A3 GND A2 A1 A0 TEST nWRL nWRH nRD nRESET nRAS VDD VDD nCASL nCASH nDRAMOE nDRAMWR nXRAMSEL nXROMSEL nXMEMSEL X_PCLK SECLK SEDO GPIO29 UART_TXD GND GND UART_RXD nENS CLKS nDTSRB nASTRB nWRITE P9 P5 P4 Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO31 GPIO30 GPIO29 GPIO28 GPIO Pins Pin Type Output Output GND Output Output Output Input Output Output Output Input Output Power Power Output Output Output Output Output Output Output Bidir Bidir Bidir Bidir Output GND GND Input Output Output Output Output Output Output Output Output GPIO & Fast EPP Pin Chip Revision 1.1 External Memory Address Bus, A4 External Memory Address Bus, A3 Digital ground External Memory Address Bus, A2 External Memory Address Bus, A1 External Memory Address Bus, A0 No Connection, MFG test only Active LOW, Write to lower bank of External SRAM Active LOW, Write to upper bank of External SRAM Active LOW, Read from External SRAM or ROM Master Reset. SL11R Device active low reset input. Active LOW, DRAM Row Address Select +3.3 VDC Supply +3.3 VDC Supply Active LOW, DRAM Column Low Address Select Active LOW, DRAM Column High Address Select Active LOW, DRAM Output Enable Active LOW, DRAM Write Active LOW, select external SRAM (16 bit) Active LOW, select external ROM Active LOW, select external Memory bus, external SRAM, DRAM, ROM or any memory mapped device See register 0xC006 for more information SECLK, Serial EEPROM clock, or GPIO31 SEDO, Serial flash EPROM Data, or GPIO30 This pin requires a 5-k pull-up. GPIO29 UART Transmit Data (out), or GPIO28 Digital ground Digital ground UART Receive Data (in), or GPIO27 Serial EPROM control signal Serial EPROM Clock EPP Data Strobe EPP Address Strobe EPP Write Strobe P Register P Register or PWR_OFF P Register Page 23 of 27 Document #: 38-08007 Rev. ** SL11RIDE Table 10-5. Fast EPP Pin Assignment and Description (continued) Pin Name VDD P3 P2 P1 GND P6 P7 P8 GPIO12 DATAS VREQ WAIT VDD1 DATA+ DATA- GND1 INTR SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 VDD Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO18 GPIO17 GPIO16 GPIO Pins Pin Type Power Output Output Output GND Output Output Output Bidir Bidir Input Bidir Power Bidir Bidir GND Input Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Power GPIO & Fast EPP Pin Chip Revision 1.1 +3.3 VDC Supply P Register or USB_PU (USB DATA+ pull up) P Register P Register Digital ground P Register P Register P Register GPIO12 DATA Strobe for Serial EPROM TBD EPP WAIT signal USB +3.3 VDC Supply. USB Differential DATA Signal High Side USB Differential DATA Signal Low Side USB Digital Ground EPP INTR pin EPP Data bit 7 EPP Data bit 6 EPP Data bit 5 EPP Data bit 4 EPP Data bit 3 EPP Data bit 2 EPP Data bit 1 EPP Data bit 0 +3.3 VDC Supply 10.7 Design ATAPI/IDE Device Behaves Like Floppy Disk Drive This design applies to small and low power consumption ATAPI/IDE devices such as Compact Flash, CLIK, MicroDrives, and Smart Media cards. This is an advantage for users to exchange media cards (i.e. MP3) from the SL11RIDE board without plugging or unplugging the USB cable. This requires three free GPIO signals: * GPIO 19-CD_DET: Card Detect * GPIO 25-PWC_RESET: Power Hardware Reset * GPIO 26-PWC: Power Control Document #: 38-08007 Rev. ** Page 24 of 27 SL11RIDE VCC MMBT2907A CFVCC 12K + FROM SL11RIDE 220 0.1 F 10 F 10K Figure 10-1. Compact Flash Design Note Table 10-6. Power Switch Operation Power switch operation PWC Signal High Low PVCC Output OFF ON Table 10-7. Compact Flash Design Name VCC RPU RPURS RRS CD_DET PWC_RESET PWC PVCC +5V from USB Power or external power 10-k pull-up resistor 10-k pull-up resistor 1-k series resistor (This depends on transistor requirement) Card detection uses to detect card present or not. It need 10k pull-up to +3.3VDC. Hardware Reset to the card after power on Power control use to turn power on/off when the card insert/remove Power supply to Compact Flash. It must provide enough current and voltage to the card. Description 10.8 10.8.1 CPU Speed Control Speed Control Register (0xC008: R/W) The Speed Control Register allows the SL11R processor to operate at a number of speed selections. A four-bit divider (SPD3-0 + 1) selects the speed as shown below. Speed will also depend on the clock multiplier. See Configuration Register (0xC006: R/W) for more information. D15-D4 0 D3 SPD3 D2 SPD2 D1 SPD1 D0 SPD0 D3-D0 SPD3-SPD0 Speed selection bits Document #: 38-08007 Rev. ** Page 25 of 27 SL11RIDE SPD3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D15-D4 Note: Upon reset, the lowest speed is selected for low power operation. The SL11R BIOS will configure the clock to 24 MHz as part of its initialization. Reserved SL11R Speed 48.00 MHz. 24.00 MHz. 16.00 MHz. 12.00 MHz. 09.60 MHz. 08.00 MHz. 06.86 MHz. 06.00 MHz. 05.33 MHz. 04.80 MHz. 04.36 MHz. 04.00 MHz. 03.69 MHz. 03.42 MHz. 03.20 MHz. 03.00 MHz. should be set to all zeros. Document #: 38-08007 Rev. ** Page 26 of 27 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. SL11RIDE 11.0 Revision History Document Title: SL11RIDE USB to IDE/ATAPI Solution Document Number: 38-08007 REV. ** ECN NO. 110566 ISSUE DATE 12/14/01 ORIG. OF CHANGE BHA DESCRIPTION OF CHANGE Converted to Cypress Format from ScanLogic Document #: 38-08007 Rev. ** Page 27 of 27 |
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